Quartus SDC Constraints Cheatsheet

Timing constraints for Intel/Altera FPGAs — same TCL dialect, different details.

Clocks

# Primary clock: 50 MHz oscillator
create_clock -period 20.000 -name clk50 [get_ports clk50]

# PLL output clocks: one line derives them all (Quartus Prime)
derive_pll_clocks
derive_clock_uncertainty          # ALWAYS include this line

# Manually generated clock (fabric divider - avoid if you can)
create_generated_clock -name clk_div2 -source [get_ports clk50] \
    -divide_by 2 [get_registers div_reg]

# Asynchronous groups
set_clock_groups -asynchronous \
    -group {clk50} \
    -group {pll|pll_inst|altera_pll_i|outclk_wire[0]}

I/O timing

# External device clocks data out 2-5 ns after its clock
set_input_delay  -clock clk50 -min 2.0 [get_ports din[*]]
set_input_delay  -clock clk50 -max 5.0 [get_ports din[*]]

set_output_delay -clock clk50 -max 3.0  [get_ports dout[*]]
set_output_delay -clock clk50 -min -1.0 [get_ports dout[*]]

# Truly asynchronous pins: cut them explicitly
set_false_path -from [get_ports rst_n]
set_false_path -to   [get_ports led[*]]

Path exceptions

set_false_path -from [get_registers *cfg_static*]

# Bounded CDC latency (preferred over false path for synchronizers)
set_max_delay -from [get_registers src_reg] -to [get_registers meta_ff0] 8.0

set_multicycle_path -setup -from [get_registers a_reg[*]] \
    -to [get_registers p_reg[*]] 2
set_multicycle_path -hold  -from [get_registers a_reg[*]] \
    -to [get_registers p_reg[*]] 1

Quartus vs Vivado translation table

Concept Quartus SDC Vivado XDC
Derive PLL clocks derive_pll_clocks automatic
Clock uncertainty derive_clock_uncertainty automatic
Registers get_registers name get_cells name_reg
Pin assignment .qsf file (set_location_assignment) in XDC (PACKAGE_PIN)
I/O standard .qsf (set_instance_assignment) in XDC (IOSTANDARD)

Pin + I/O standard live in the .qsf, not the SDC:

set_location_assignment PIN_R8 -to clk50
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk50

Verifying in TimeQuest / Timing Analyzer

report_clocks -panel_name Clocks
report_timing -setup -npaths 10 -detail full_path
report_ucp                        # unconstrained paths
report_sdc                        # what actually got applied
check_timing

Rules of thumb