LFSR Generator
Generate a maximal-length linear feedback shift register in Verilog or VHDL for any width from 2 to 64 bits, Fibonacci (XNOR) or Galois (XOR) form, using the standard XAPP052 tap table.
Results
- Taps (1-indexed, XAPP052)
- 16, 15, 13, 4
- Period
- 2^16 - 1 = 65,535
- Lockup state
- all-ones (XNOR)
Notes
- Fibonacci XNOR form lets you reset to zero safely; Galois form has shorter feedback paths and usually higher fmax.
- An LFSR is a fast pseudo-random sequence / counter, not a cryptographic RNG.
- Tip: an LFSR makes a cheap event counter when you don't need the count in binary (compare against a precomputed LFSR value).
// 16-bit maximal-length LFSR (fibonacci), period 2^16-1 = 65535
// Taps (XAPP052): [16, 15, 13, 4]. Generated by libfpga.com/tools/lfsr-generator
module lfsr16_fib (
input wire clk,
input wire rst, // sync reset to a valid seed
input wire en,
output reg [15:0] lfsr
);
// XNOR feedback: all-zeros is a valid state, all-ones locks up.
wire fb = ~(lfsr[15] ^ lfsr[14] ^ lfsr[12] ^ lfsr[3]);
always @(posedge clk) begin
if (rst) lfsr <= 16'd0;
else if (en) lfsr <= {lfsr[14:0], fb};
end
endmodule-- 16-bit maximal-length LFSR (fibonacci), period 2^16-1
-- Taps (XAPP052): [16, 15, 13, 4]. Generated by libfpga.com/tools/lfsr-generator
library ieee;
use ieee.std_logic_1164.all;
entity lfsr16_fib is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
q : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of lfsr16_fib is
signal lfsr : std_logic_vector(15 downto 0) := (others => '0');
signal fb : std_logic;
begin
q <= lfsr;
fb <= not (lfsr(15) xor lfsr(14) xor lfsr(12) xor lfsr(3));
process (clk) begin
if rising_edge(clk) then
if rst = '1' then
lfsr <= (others => '0');
elsif en = '1' then
lfsr <= lfsr(14 downto 0) & fb;
end if;
end if;
end process;
end architecture;About this tool
A linear feedback shift register steps through a pseudo-random sequence using nothing but a shift register and a couple of XOR gates, with the right taps, it visits every non-lockup state before repeating (period 2n−1). That makes LFSRs the cheapest test-pattern and noise generators in digital logic, and a sneaky-fast substitute for a binary counter when you only need 'count N events', not the number itself. This generator uses the maximal-length taps from Xilinx application note XAPP052 and emits either form: Fibonacci (XNOR feedback, resets safely to zero) or Galois (shorter feedback path, usually better fmax).
Cores that use this
Open FPGA IP from the registry you can drop in instead of building from scratch.