Learn FPGA design by example
A hands-on path from logic gates to a working ALU. Every lesson comes in Verilog, VHDL and MyHDL, explains the ideas, and includes a real simulated waveform, generated by actually running the code. Then you can open any lesson in a playground, change it, and see your own waveform in seconds. No signup, no installs.
Basics
01 · Logic Gates
Where every design begins: describing combinational logic with `assign`.
02 · Multiplexers
The hardware `if`: routing one of several inputs to an output.
03 · Latches vs. Flip-Flops
The two kinds of memory, and why one of them is usually a bug.
04 · Counters
Your first real sequential circuit: a register plus an adder, in a loop.
05 · Shift Registers
Serial-to-parallel, parallel-to-serial, and the LED chaser.
Intermediate
06 · Adders
From one full adder to real arithmetic, and why you should just write `+`.
07 · Multipliers
Shift-and-add, DSP blocks, and the width rule everyone trips over.
08 · State Machines
Giving a circuit a memory of \"where it is\": a serial pattern detector.
Capstone
Playgrounds
The Verilog playground compiles and simulates your code with Icarus Verilog on our server and renders the waveform, the fastest way to try an idea without installing anything. Prefer Python? The MyHDL playground lets you describe hardware in Python and simulate it the same way (see the MyHDL introduction).
Ready to test yourself?
The practice challenges hand you a spec and a locked testbench, write the module until it passes. Instant grading, progress saved on your device.