Verilog playground

Your code is compiled and simulated with Icarus Verilog and the waveform rendered from the VCD. Keep $dumpfile/$dumpvars in the testbench and always $finish. Limits: 16 KB per file, ~5 s of simulation, no file or system tasks.

Design (design.v)

// Combinational (DSP) multiply next to a shift-and-add sequential one.
module multipliers (
    input  wire       clk,
    input  wire       rst,
    input  wire       start,
    input  wire [3:0] a, b,
    output wire [7:0] product_comb,   // instant: uses a DSP block
    output reg  [7:0] product_seq,    // 4 clocks: one adder
    output reg        busy,
    output reg        done
);
    assign product_comb = a * b;

reg [7:0] acc, addend;
    reg [3:0] multiplier;
    reg [2:0] count;

always @(posedge clk) begin
        done <= 1'b0;
        if (rst) begin
            busy <= 1'b0;
            product_seq <= 8'd0;
        end else if (start && !busy) begin
            busy       <= 1'b1;
            acc        <= 8'd0;
            addend     <= {4'd0, a};
            multiplier <= b;
            count      <= 3'd0;
        end else if (busy) begin
            if (multiplier[0])
                acc <= acc + addend;
            addend     <= addend << 1;
            multiplier <= multiplier >> 1;
            count      <= count + 3'd1;
            if (count == 3'd3) begin
                busy        <= 1'b0;
                done        <= 1'b1;
                product_seq <= multiplier[0] ? acc + addend : acc;
            end
        end
    end
endmodule

Testbench (tb.v)

Notes

Start from a lesson: every Learn page has an "open in playground" button that preloads its code.
The design file may contain multiple modules; the testbench must be a module with no ports (conventionally tb).
Simulation shows behavior, not timing — code that simulates perfectly can still be unsynthesizable or fail timing on real hardware.