Verilog playground

Your code is compiled and simulated with Icarus Verilog and the waveform rendered from the VCD. Keep $dumpfile/$dumpvars in the testbench and always $finish. Limits: 16 KB per file, ~5 s of simulation, no file or system tasks.

Notes

• Start from a lesson: every Learn page has an "open in playground" button that preloads its code.
• The design file may contain multiple modules; the testbench must be a module with no ports (conventionally tb).
• Simulation shows behavior, not timing — code that simulates perfectly can still be unsynthesizable or fail timing on real hardware.