AXI4 / AXI-Lite / AXI-Stream Cheatsheet
The signals, the handshake rules, and the mistakes everyone makes once.
The one rule that is 90% of AXI
Every channel moves data when VALID && READY on the same rising edge.
- VALID must not wait for READY. A source asserts VALID when it has data and holds it (payload unchanged!) until the beat transfers.
- READY may wait for VALID, may be held high always, may toggle freely.
- Once VALID is high, dropping it before READY arrives is a protocol violation.
- No combinational path from READY to VALID in the same module (deadlock and timing-loop bait).
The three flavors
| AXI4-Lite | AXI4 (full) | AXI4-Stream | |
|---|---|---|---|
| Purpose | control registers | memory, DMA | unidirectional data flow |
| Channels | 5 (AW W B AR R) | 5, with bursts | 1 (T*) |
| Burst | none (1 beat) | 1-256 beats | unlimited stream |
| Typical use | CSR blocks | DDR access | samples, packets, video |
AXI4-Lite signal set (the whole thing)
Write: AWADDR AWVALID AWREADY | WDATA WSTRB WVALID WREADY | BRESP BVALID BREADY
Read: ARADDR ARVALID ARREADY | RDATA RRESP RVALID RREADY
WSTRB[n]= byte lane n of WDATA is valid. Honor it in register writes.BRESP/RRESP:00OKAY,10SLVERR,11DECERR. Lite slaves mostly return OKAY or SLVERR.- AW and W can arrive in either order — a robust slave waits for both.
- Need a generated register block? Use the register-map generator.
AXI4 (full) additions
- Bursts:
AxLEN(beats−1, 0–255),AxSIZE(bytes/beat, log2),AxBURST(01INCR almost always;10WRAP for cache lines). WLAST/RLASTmark the final beat — slaves check, masters must set.AxIDallows multiple outstanding transactions; responses with the same ID stay ordered, different IDs may interleave (reads) or reorder.- 4 KB rule: a burst must not cross a 4 KB address boundary.
- No
WSTRBgaps mid-burst unless you enjoy interconnect edge cases.
AXI4-Stream essentials
TDATA TVALID TREADY TLAST [TKEEP TUSER TID TDEST]
TLASTmarks packet end (line end in video, frame end in DMA).TKEEPmarks valid bytes in the final beat of unaligned packets.- No addresses, no responses: backpressure is TREADY, full stop.
- A skid buffer (register slice) is the standard fix for TREADY timing.
Handshake bugs hall of fame
- Combinational READY→VALID loop between two modules: works in sim with one ordering, deadlocks in another.
- Changing WDATA while WVALID is high because "READY was low anyway" — the interconnect may have already sampled a lane.
- Assuming AW before W. Xilinx DMA IP sends them together; some masters send W first.
- Forgetting WLAST on a custom master: the slave waits forever for the beat that never comes.
- One outstanding transaction assumed: full-AXI masters can issue several AR before the first R returns.
- Reset: VALIDs must be low the cycle after reset deasserts — ARESETn is active-low and asynchronous assert is common, so synchronize the deassert.
Debug checklist
WVALID && !WREADYstuck for thousands of cycles → who owns the stall? Walk READY backwards through the interconnect.BVALID && !BREADYstuck → your master forgot to accept responses.- Data corrupted only under load → look for a VALID-high payload change.
- ILA trigger recipe:
(AWVALID && !AWREADY)held N cycles catches most write-path deadlocks.