Clock Divider Calculator
Find the best integer divide ratio from an input clock to a target frequency, see the error in ppm, and get a clean Verilog divider - plus the clock-enable pattern you should probably use instead.
Results
- Exact ratio needed
- 100
- Best integer divider
- /100
- Actual output
- 1 MHz
- Error
- +0.0 ppm
Nearby dividers
| Divide by | Output | Error | Duty cycle |
|---|---|---|---|
| 99 | 1.0101 MHz | +10,101.0 ppm | ~49.5% |
| 100 | 1 MHz | +0.0 ppm | 50% |
| 101 | 0.990099 MHz | -9,901.0 ppm | ~49.5% |
Notes
- Prefer a clock enable over a divided clock whenever the slow logic stays in the same domain - see the second code block.
- For exact or fractional ratios use a PLL/MMCM; a plain counter can only hit f_in / N.
// Divide 100 MHz by 100 -> 1 MHz
// Generated by libfpga.com/tools/clock-divider
module clk_div #(
parameter integer DIV = 100 // must be >= 2
) (
input wire clk_in,
input wire rst,
output reg clk_out
);
localparam integer CW = $clog2(DIV);
reg [CW-1:0] cnt;
always @(posedge clk_in) begin
if (rst) begin
cnt <= 0;
clk_out <= 1'b0;
end else if (cnt == DIV/2 - 1 + (clk_out ? DIV % 2 : 0)) begin
cnt <= 0;
clk_out <= ~clk_out;
end else begin
cnt <= cnt + 1'b1;
end
end
endmodule// Preferred: clock ENABLE at 1/100 rate - keeps everything in one
// clock domain, no CDC, and the tools can time it properly.
reg [$clog2(DIV)-1:0] div_cnt;
reg tick; // 1-cycle pulse every DIV cycles
always @(posedge clk) begin
if (rst) begin
div_cnt <= 0;
tick <= 1'b0;
end else if (div_cnt == DIV-1) begin
div_cnt <= 0;
tick <= 1'b1;
end else begin
div_cnt <= div_cnt + 1'b1;
tick <= 1'b0;
end
end
// then: always @(posedge clk) if (tick) ... your slow logic ...About this tool
A counter can only divide a clock by an integer, so the first question is which integer lands closest to your target and how many ppm off that is — this calculator answers both and shows the neighbors. The second question is whether you should divide the clock at all: a fabric-generated clock burns a global routing resource, complicates timing analysis, and creates a CDC at every boundary. If the slow logic can stay in the fast domain, use the clock-enable pattern in the second code block instead — one domain, no CDC, and the tools time it automatically. Save real derived clocks for when you truly need them, and prefer a PLL/MMCM for exact or fractional ratios.