PLL / MMCM Calculator
Compute MMCM/PLL settings for Xilinx 7-series: multiply/divide values for a target output frequency, VCO legality check, error in ppm, alternative settings, and a ready MMCME2_BASE/PLLE2_BASE Verilog instantiation.
Results
- M / D / O
- 11.875 / 1 / 9.5
- VCO
- 1187.50 MHz (range 600-1200)
- Actual output
- 125 MHz
- Error
- +0.0 ppm
Best settings (top 5)
| M | D | O | VCO | Output | Error |
|---|---|---|---|---|---|
| 11.875 | 1 | 9.5 | 1187.50 MHz | 125 MHz | +0.0 ppm |
| 46.875 | 4 | 9.375 | 1171.88 MHz | 125 MHz | +0.0 ppm |
| 23.125 | 2 | 9.25 | 1156.25 MHz | 125 MHz | +0.0 ppm |
| 45.625 | 4 | 9.125 | 1140.62 MHz | 125 MHz | +0.0 ppm |
| 11.25 | 1 | 9 | 1125.00 MHz | 125 MHz | +0.0 ppm |
Notes
- Exact ratio achieved (0 ppm).
- Phase-detector input = f_in / D = 100.000 MHz (legal range 10-450 MHz).
- Among equal-error solutions, prefer the higher VCO for lower output jitter.
- Remaining MMCM/PLL outputs (CLKOUT1-6) divide the same VCO by integers - plan all your clocks around one VCO before committing.
// MMCME2_BASE: 100 MHz in, CLKOUT0 = in * 11.875 / (1 * 9.5)
// Generated by libfpga.com/tools/pll-calculator
MMCME2_BASE #(
.CLKIN1_PERIOD (10.000),
.CLKFBOUT_MULT_F (11.875), // M
.DIVCLK_DIVIDE (1), // D
.CLKOUT0_DIVIDE_F (9.5), // O
.BANDWIDTH ("OPTIMIZED")
) mmcm_inst (
.CLKIN1 (clk_in),
.CLKFBIN (clkfb),
.CLKFBOUT (clkfb),
.CLKOUT0 (clk_out_unbuf),
.LOCKED (locked),
.RST (rst),
.PWRDWN (1'b0)
);
BUFG bufg_out (.I(clk_out_unbuf), .O(clk_out));
// Feedback needs no BUFG when only used internally like this.About this tool
An MMCM or PLL multiplies the input clock up to a VCO frequency (f_in × M / D) and divides it back down per output (÷O). The catch is that the VCO must stay inside a datasheet window that depends on primitive and speed grade, and the phase detector input (f_in / D) has its own limits — so not every ratio is reachable, and some reachable ratios have several solutions that differ in jitter (higher VCO is generally better). This calculator searches the legal space, ranks by frequency error then VCO, and emits the matching MMCME2_BASE/PLLE2_BASE instantiation. Same math the Clocking Wizard does, without opening Vivado. UltraScale note: ranges differ (e.g. MMCME3/4 VCO 800-1600 MHz), so re-check before porting.