UART Baud Rate Calculator
Compute the UART clock divisor for any system clock and baud rate, the actual resulting baud rate, the error percentage against the +/-2% budget, and a full table across standard baud rates.
Results
- Divisor
- 54
- Actual baud
- 115,740.74
- Error
- +0.4694% (OK)
- Tick frequency
- 1.85185 MHz (16x oversample)
All standard bauds @ 100 MHz
| Baud | Divisor | Actual | Error | Verdict |
|---|---|---|---|---|
| 9,600 | 651 | 9,600.6 | +0.006% | ok |
| 19,200 | 326 | 19,171.8 | -0.147% | ok |
| 38,400 | 163 | 38,343.6 | -0.147% | ok |
| 57,600 | 109 | 57,339.4 | -0.452% | ok |
| 115,200 | 54 | 115,740.7 | +0.469% | ok |
| 230,400 | 27 | 231,481.5 | +0.469% | ok |
| 460,800 | 14 | 446,428.6 | -3.119% | avoid |
| 921,600 | 7 | 892,857.1 | -3.119% | avoid |
| 1,000,000 | 6 | 1,041,666.7 | +4.167% | avoid |
| 3,000,000 | 2 | 3,125,000.0 | +4.167% | avoid |
Notes
- Budget: both ends may be off; keeping each side within +/-2% keeps the last data bit sampled within its window over a 10-bit frame.
- RX should oversample (16x is conventional) so it can find the start bit edge and sample mid-bit; TX only needs a 1x baud tick.
Verilog tick generator
// 16x-oversample tick generator, divisor 54
// Generated by libfpga.com/tools/uart-baud
localparam integer BAUD_DIV = 54;
reg [$clog2(BAUD_DIV)-1:0] baud_cnt;
reg baud_tick;
always @(posedge clk) begin
if (rst) begin
baud_cnt <= 0;
baud_tick <= 1'b0;
end else if (baud_cnt == BAUD_DIV-1) begin
baud_cnt <= 0;
baud_tick <= 1'b1;
end else begin
baud_cnt <= baud_cnt + 1'b1;
baud_tick <= 1'b0;
end
endAbout this tool
A UART has no clock wire: both ends time bits from their own oscillators, so the receiver's clock error accumulates across the frame. Over a 10-bit frame (start + 8 data + stop), staying within about ±2% per side keeps the final bit sampled inside its window. This calculator finds the integer divisor from your system clock (with 16x oversampling for a receiver, or 1x for a transmitter), reports the exact error, and flags combinations that won't work — the classic trap being a clock that divides beautifully to 9600 baud but lands 3% off at 921600.