Verilog linter
Paste Verilog or SystemVerilog and get
verilator --lint-only -Wall findings with line numbers —
width mismatches, latch inference, unused signals, blocking/non-blocking
mixups — the checks that catch bugs before simulation does.
About this tool
Verilator's linter is the strictest freely available Verilog checker —
many teams gate CI on it. It catches the classics early: a 4-bit adder
feeding an 8-bit register (WIDTHEXPAND), an
always @* that forgot a branch (LATCH), signals
driven from two blocks (MULTIDRIVEN), blocking assignments
in sequential logic (BLKSEQ). Lint is complementary to
simulation: the playground shows what your
code does; the linter flags what it might do differently
than you think. Run both.