Block RAM Estimator
Estimate block RAM usage for a memory of any width and depth on AMD/Xilinx 7-series and UltraScale, Intel M20K, Lattice ECP5 and iCE40: best aspect-ratio tiling, block count, utilization, and URAM comparison where relevant.
Results
- Memory
- 32 x 4,096 = 131,072 bits (16.0 KiB)
- Best tiling
- 4 x BRAM36 in 1024x36 mode
- Utilization
- 89% of the consumed blocks
- URAM alternative (UltraScale+ only)
- 1 x URAM288 (4Kx72 fixed)
All aspect ratios (BRAM36 (RAMB36E1/E2))
| Mode (depth x width) | Grid | Blocks | Utilization |
|---|---|---|---|
| 1024x36 | 1 wide x 4 deep | 4 | 89% |
| 2048x18 | 2 wide x 2 deep | 4 | 89% |
| 4096x9 | 4 wide x 1 deep | 4 | 89% |
| 512x72 | 1 wide x 8 deep | 8 | 44% |
| 8192x4 | 8 wide x 1 deep | 8 | 44% |
| 16384x2 | 16 wide x 1 deep | 16 | 22% |
| 32768x1 | 32 wide x 1 deep | 32 | 11% |
Notes
- 512x72 is SDP-only; x9/x18/x36/x72 use the parity bits.
- Depths beyond one block add output muxing (or cascade latency on UltraScale/M20K) - register the output.
- Synthesis may split differently for timing; treat this as the lower bound the tools aim for.
About this tool
Block RAMs aren't a pool of bits — they're fixed-size blocks with a menu of native aspect ratios, and your memory gets tiled out of whole blocks. A 4K×9 memory fits one BRAM36 exactly; make it 4K×10 and you pay two. That cliff-edge behavior is why back-of-envelope bit math (width × depth / block size) routinely underestimates by 2×. This tool evaluates every native aspect ratio and reports the cheapest tiling, its real utilization, and the alternatives — so you can nudge a width or depth before synthesis tells you the design doesn't fit. Depth beyond a single block also costs output muxing or cascade latency; keep an output register for timing either way.