Hello, LibFPGA: free tools that make FPGA design flow

Every FPGA project runs on the same small calculations. How deep does this FIFO need to be? What are the taps for a 24-bit LFSR? What's the divisor for 115200 baud at 83.333 MHz, and is the error small enough? What does -2FGG484I mean on this part number?

Getting each one right, fast, is what keeps a design day in flow, and getting one slightly wrong is what costs a day in the lab. We built tools so you always get them right, instantly.

LibFPGA is a collection of small, free, instant tools that answer exactly these questions, and show their math so you can trust and verify them:

• FIFO Depth Calculator: burst analysis with CDC slack and the reasoning written out.
• Parallel CRC Generator: synthesizable Verilog and VHDL for any polynomial and data width. The generator is verified against a bit-serial reference implementation in our test suite.
• LFSR Generator: maximal-length taps (XAPP052) for widths 2–64, Fibonacci or Galois, with lockup-safe reset values.
• UART Baud Calculator, Clock Divider, Fixed-Point Converter, Gray Code and Timing Converter.

Three design decisions worth calling out:

Results live in the URL. Run a calculation and the address bar contains your inputs. Paste it in a code review, a Slack thread, or a commit message, your teammate sees exactly what you computed.

Everything states its assumptions. A FIFO depth without the burst model behind it is a superstition. Each tool prints the formula and the caveats (reflection conventions for CRC, lockup states for LFSRs, the ±2% baud budget).

No signup required, ever. Our own analytics are aggregate counters, one number per page per day; anything beyond that is disclosed plainly in the privacy policy.

There's also a growing reference section (Verilog, VHDL, XDC, SDC, part-number decoding) and a dev-board picker.

If a tool you want is missing, tell us: hello@libfpga.com. The roadmap is literally ranked by what people ask for and use.