A 3-to-8 decoder with enable: when en is high, output bit addr
is 1 and all others are 0. When en is low, all outputs are 0.
| Port | Dir | Width | Meaning |
|---|---|---|---|
| addr | in | 3 | which output to raise |
| en | in | 1 | enable |
| out | out | 8 | one-hot (or all zero) |
Hint: a shift can do this in one line.
`timescale 1ns/1ps
module tb;
reg [2:0] addr; reg en; wire [7:0] out;
integer i, errors=0; reg [7:0] want;
challenge dut (.addr(addr), .en(en), .out(out));
initial begin
$dumpfile("wave.vcd"); $dumpvars(0, tb);
for (i = 0; i < 16; i = i + 1) begin
{en, addr} = i[3:0]; #5;
want = en ? (8'd1 << addr) : 8'd0;
if (out !== want) begin
errors = errors + 1;
$display("FAIL: en=%b addr=%0d -> out=%b (want %b)",
en, addr, out, want);
end
end
if (errors == 0) $display("TB PASS");
else $display("TB FAIL (%0d errors)", errors);
$finish;
end
endmodule