What's new on LibFPGA

2026-07-04 · libfpga-myhdl v0.3.0

Co-simulation: the MyHDL library now runs its generated Verilog through Icarus and proves it behaves identically to the Python model, not just that it converts. Plus a round-robin arbiter and a pulse-CDC block. 12 blocks.

UART and SPI in MyHDL: uart_tx/uart_rx (verified by a tx→rx loopback) and spi_master (against a behavioral slave). 10 blocks now; each converts to Verilog+VHDL with the Verilog compiled in CI.

New repo: libfpga-myhdl — the Python companion to the library: 7 building blocks in MyHDL, each with a self-checking pytest suite and a Verilog/VHDL conversion check (the generated Verilog is compiled in CI). Pairs with the new MyHDL playground.

Formal verification: five modules now carry machine-checked proofs (yosys + z3, by induction) that their protocol and safety contracts hold for every input, for all time, not just on the test vectors. FIFO invariants, arbiter one-hot grants, skid-buffer handshake safety, and more.

lfpga_i2c_master: a single-master 7-bit I2C controller with byte-level commands and open-drain pin control. 29 modules in the library now.

The neural micro-kit: fixed-point math (resize/mult/add), a multiply-accumulate cell, ReLU, and a MLP generator that turns a trained network into pipelined, self-verifying Verilog. 28 modules total.

New educational repo: fpga-neuron: a neural network from first principles to FPGA hardware. Train XOR in dependency-free Python, quantize to Q4.4, synthesize a fully combinational network (832 LUT4s, zero flip-flops), and prove it with a 293-vector exhaustive testbench. Schematics, loss curves and decision-boundary plots included.

Seven utility modules: popcount, priority encoder, one-hot mux, edge detect, debounce, PWM, and a fractional-rate clock enable, the small blocks everyone rewrites, now verified once for everybody. 21 modules total.

The library shipped its core: 14 verified modules, sync & async FIFOs, skid buffer, round-robin arbiter, UART TX/RX, SPI master, parallel CRC, LFSR, Gray codecs, and an AXI-Lite bridge. Every one with a self-checking testbench, clean lint, and honest resource stats. Module table.

Practice challenges: 10 graded Verilog exercises with instant in-browser grading, failure waveforms, and progress saved on your device. From logic gates to a working FIFO.
Site search: every tool, lesson, challenge, term and article, from the ⌕ in the menu.
The libfpga library went live on GitHub: MIT-licensed, verified CDC primitives, CI on the open toolchain. FIFOs and friends next.
Lesson progress tracking on the course; a fresh home page; the chip logo and four-color look everywhere.
New article: Datacenters in space, SEUs, TMR and scrubbing, with NASA imagery.

LibFPGA.com launched with 15 free tools, a 9-lesson hands-on HDL course, and the live Verilog playground.
The playground grew lint (Verilator) and synthesis estimates (Yosys), plus shareable snippet links.
Online Verilog linter, an FPGA glossary (18 terms), 8 cheatsheets, and 13 articles including FPGAs for AI and FPGAs in high-frequency trading.
Every tool doubles as a JSON API.