libfpga — the library
An MIT-licensed, vendor-neutral library of FPGA building blocks, developed in the open at github.com/libfpga/libfpga. Plain Verilog-2005 that synthesizes on Vivado, Quartus and the open Yosys flow — with a quality bar most libraries only claim.
Every module is verified
CI enforces three gates on the fully open toolchain: a
self-checking testbench (Icarus Verilog),
lint-clean under Verilator -Wall, and a
Yosys synthesis check with honest LUT/FF resource
stats. If it's in the library, it passed all three.
Documented like a textbook
Each module's header explains what it is, when to use it, and its gotchas — and pairs with this site's course, glossary and playground, where you can simulate library code in your browser.
Modules — v0.1.0
| Module | What it is | Cost* |
|---|---|---|
| CDC | ||
lfpga_sync_bit | N-flop synchronizer for one async level bit | 2 FF |
lfpga_sync_pulse | Toggle-based pulse crossing, either direction | 2 LUT4 + 4 FF |
lfpga_reset_sync | Reset: async assert, sync deassert | 2 FF |
| FIFOs & streams | ||
lfpga_fifo_sync | Synchronous show-ahead FIFO with count | 154 LUT4 + 145 FF |
lfpga_fifo_async | Dual-clock FIFO, gray pointers (Cummings) | 154 LUT4 + 168 FF |
lfpga_skid_buffer | valid/ready register slice, full throughput | 16 LUT4 + 18 FF |
lfpga_arbiter_rr | Round-robin arbiter, one-hot grant | 18 LUT4 + 4 FF |
| Serial | ||
lfpga_uart_tx | UART transmitter, 8N1, valid/ready | 48 LUT4 + 24 FF |
lfpga_uart_rx | UART receiver, mid-bit sampling, glitch reject | 63 LUT4 + 32 FF |
lfpga_spi_master | SPI master, mode 0, full duplex | 32 LUT4 + 27 FF |
| Math & bus | ||
lfpga_crc | Parallel CRC, any polynomial, word/clock | 17 LUT4 + 16 FF |
lfpga_lfsr | Maximal-length LFSR (XAPP052 taps) | 1 LUT4 + 16 FF |
lfpga_gray | Binary ↔ Gray converters | 3 LUT4 |
lfpga_axil_bridge | AXI4-Lite slave → simple register bus | 5 LUT4 + 80 FF |
*Generic Yosys synth -lut 4 mapping at default
parameters — the same estimate the
playground's synth button gives you. All
sources on GitHub —
v0.1.0 release.
Roadmap
- v0.1 — shipped (2026-07-04): everything in the table above.
- v0.2 — the neural micro-kit: INT8 MAC array, activations, weight loaders, and a complete quantized MLP inference core (why FPGAs are shaped like neural networks).
- v0.3 — formal properties for the protocol modules, FuseSoC packaging, board demos.
Want a module prioritized? Open an issue or drop a line in the tool request box — the roadmap is ranked by real requests.