LibFPGA Library

An MIT-licensed, vendor-neutral library of FPGA building blocks, developed in the open at github.com/libfpga/libfpga. Plain Verilog-2005 that synthesizes on Vivado, Quartus and the open Yosys flow, with a quality bar most libraries only claim.

Every module is verified

CI enforces four gates on the fully open toolchain: a self-checking testbench (Icarus), lint (Verilator -Wall), a Yosys synthesis check with honest LUT/FF stats, and formal proofs (yosys + z3, by induction) on the safety-critical modules, contracts that hold for every input, for all time.

Documented like a textbook

Each module's header explains what it is, when to use it, and its gotchas, and pairs with this site's course, glossary and playground, where you can simulate library code in your browser.

Learn the patterns first

New to a building block? The RTL Recipes explain each one, run live in your browser, and link straight back to the verified module here, so you can understand the pattern, then ship the packaged version.

Two-flop synchronizer

Safely bring an asynchronous signal into your clock domain.

Button debouncer

Reject the mechanical bounce on a switch or button.

Edge detector

Turn a level into a one-clock pulse on its rising (or falling) edge.

Clock divider (do it with an enable)

Run logic at a slower rate without gating the clock.

One-hot state machine

Give every state its own flip-flop for fast, readable FSMs.

PWM generator

Dim an LED or drive a motor with a duty-cycled pulse.

Synchronous FIFO

Buffer a stream between a producer and a consumer on one clock.

UART transmitter

Send a byte down a wire, one start bit, eight data bits, one stop bit.

Gray-code converter

Count so that only one bit ever changes at a time.

SPI master

Clock a byte out to a peripheral, MSB-first, in SPI mode 0.

CRC-8 (serial)

Catch transmission errors with a cyclic redundancy check.

Round-robin arbiter

Share one resource fairly among many requesters.

UART receiver

Recover a byte from a serial line with no shared clock.

Asynchronous FIFO

Move a data stream safely between two independent clocks.

Skid buffer

A valid/ready pipeline register that keeps full throughput under backpressure.

Priority encoder

Find the lowest set bit: index plus a valid flag.

Barrel shifter

Shift by a variable amount in a single cycle.

LFSR (pseudo-random)

Cheap pseudo-random numbers from a handful of XOR gates.

Modules, v0.2.0

Module	What it is	Cost*
CDC
`lfpga_sync_bit`	N-flop synchronizer for one async level bit	2 FF
`lfpga_sync_pulse`	Toggle-based pulse crossing, either direction	2 LUT4 + 4 FF
`lfpga_reset_sync`	Reset: async assert, sync deassert	2 FF
FIFOs & streams
`lfpga_fifo_sync`	Synchronous show-ahead FIFO with count	154 LUT4 + 145 FF
`lfpga_fifo_async`	Dual-clock FIFO, gray pointers (Cummings)	154 LUT4 + 168 FF
`lfpga_skid_buffer`	valid/ready register slice, full throughput	16 LUT4 + 18 FF
`lfpga_arbiter_rr`	Round-robin arbiter, one-hot grant	18 LUT4 + 4 FF
Serial
`lfpga_uart_tx`	UART transmitter, 8N1, valid/ready	48 LUT4 + 24 FF
`lfpga_uart_rx`	UART receiver, mid-bit sampling, glitch reject	63 LUT4 + 32 FF
`lfpga_spi_master`	SPI master, mode 0, full duplex	32 LUT4 + 27 FF
`lfpga_i2c_master`	I2C master, 7-bit, open-drain	123 LUT4 + 38 FF
Utilities
`lfpga_popcount`	Count set bits (combinational tree)	12 LUT4
`lfpga_priority_encoder`	Lowest-set-bit: one-hot + index	18 LUT4
`lfpga_onehot_mux`	AND-OR mux for one-hot selects	24 LUT4
`lfpga_edge_detect`	Rise/fall/toggle pulses	3 LUT4 + 1 FF
`lfpga_debounce`	Debouncer with press/release events	44 LUT4 + 25 FF
`lfpga_pwm`	PWM, glitch-free duty updates	33 LUT4 + 17 FF
`lfpga_clkdiv_frac`	Fractional-rate clock enable	27 LUT4 + 16 FF
Fixed-point & neural
`lfpga_fix_resize`	Requantize: shift + round + saturate	31 LUT4
`lfpga_fix_mult`	Signed fixed-point multiply, resized	240 LUT4
`lfpga_fix_add`	Fixed-point add/sub, saturating	48 LUT4
`lfpga_mac`	Signed multiply-accumulate (the NN atom)	326 LUT4 + 32 FF
`lfpga_relu`	ReLU / leaky / clipped + requantize	129 LUT4
`lfpga_barrel_shifter`	Single-cycle logical/arith shift	139 LUT4
`lfpga_bitreverse`	Reverse bit order	0 LUT4
Math & bus
`lfpga_crc`	Parallel CRC, any polynomial, word/clock	17 LUT4 + 16 FF
`lfpga_lfsr`	Maximal-length LFSR (XAPP052 taps)	1 LUT4 + 16 FF
`lfpga_gray`	Binary ↔ Gray converters	3 LUT4
`lfpga_axil_bridge`	AXI4-Lite slave → simple register bus	5 LUT4 + 80 FF

*Generic Yosys synth -lut 4 mapping at default parameters, the same estimate the playground's synth button gives you. All sources on GitHub, v0.5.0 release.

Roadmap

v0.1 + v0.2, shipped (2026-07-04): everything in the table above.
v0.3, the neural micro-kit: INT8 MAC array, activations, weight loaders, and a complete quantized MLP inference core (why FPGAs are shaped like neural networks).
v0.4, I2C master, formal properties for the protocol modules, FuseSoC packaging, board demos.

Want a module prioritized? Open an issue or drop a line in the tool request box, the roadmap is ranked by real requests.

libfpga on GitHub →

Browse this and other open cores in the FPGA core registry.

Companion example

fpga-neuron: an educational walkthrough from gradient descent to synthesized gates, a neural network that is pure combinational logic, exhaustively verified.

libfpga-myhdl: the same kind of building blocks written in MyHDL (Python), each with a pytest suite and a Verilog/VHDL conversion check. Try MyHDL in the playground.