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Output a single-cycle pulse each time din rises. pulse must be
high in exactly the first cycle where din is sampled 1 after being
sampled 0, and low otherwise. Synchronous reset clears the internal state.
| Port | Dir | Width | Meaning |
|---|---|---|---|
| clk, rst | in | 1 | clock, sync reset |
| din | in | 1 | input signal (already synchronous) |
| pulse | out | 1 | 1-cycle pulse per rising edge of din |
Hint: remember last cycle's din in a register.
`timescale 1ns/1ps
module tb;
reg clk=0, rst=1, din=0; wire pulse;
reg model_prev=0; reg want;
integer i, errors=0; reg [31:0] lfsr = 32'hACE1;
challenge dut (.clk(clk), .rst(rst), .din(din), .pulse(pulse));
always #5 clk = ~clk;
initial begin
$dumpfile("wave.vcd"); $dumpvars(0, tb);
repeat (2) @(negedge clk); rst = 0;
for (i = 0; i < 200; i = i + 1) begin
@(negedge clk);
lfsr = {lfsr[30:0], lfsr[31]^lfsr[21]^lfsr[1]^lfsr[0]};
din = lfsr[0];
#1; // combinational settle: check BEFORE the capturing edge
want = din & ~model_prev;
if (pulse !== want) begin
errors = errors + 1;
if (errors < 6)
$display("FAIL @%0t: din=%b pulse=%b want=%b",
$time, din, pulse, want);
end
@(posedge clk);
model_prev = din; // what the DUT's register captures
end
if (errors == 0) $display("TB PASS");
else $display("TB FAIL (%0d errors)", errors);
$finish;
end
endmodule