Four-Way Mux

New to this? Learn it with the Multiplexers lesson →

Build a 4:1 multiplexer: sel picks which of a,b,c,d drives y.

Port	Dir	Width	Meaning
a,b,c,d	in	1	data inputs
sel	in	2	0→a, 1→b, 2→c, 3→d
y	out	1	selected input

Any style works: case, nested ?:, or indexing.

Show the testbench (the grader)

tb.v, locked

`timescale 1ns/1ps
module tb;
    reg a, b, c, d; reg [1:0] sel; wire y;
    integer i, errors=0; reg want;
    challenge dut (.a(a), .b(b), .c(c), .d(d), .sel(sel), .y(y));
    initial begin
        $dumpfile("wave.vcd"); $dumpvars(0, tb);
        for (i = 0; i < 64; i = i + 1) begin
            {a,b,c,d,sel} = i[5:0]; #5;
            case (sel)
                2'd0: want = a; 2'd1: want = b;
                2'd2: want = c; default: want = d;
            endcase
            if (y !== want) begin
                errors = errors + 1;
                $display("FAIL: sel=%0d abcd=%b%b%b%b -> y=%b", sel, a,b,c,d, y);
            end
        end
        if (errors == 0) $display("TB PASS");
        else $display("TB FAIL (%0d errors)", errors);
        $finish;
    end
endmodule