Sequence Detector: 110

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Watch the serial input and raise detected for one cycle whenever the last three sampled bits were 1,1,0 (in that order, so detected is high in the cycle where the 0 is sampled). Overlapping patterns count: in 11010110 the pattern occurs at positions 3 and 8... check yourself with the waveform. Synchronous reset returns to the initial state.

Port Dir Width Meaning
clk, rst in 1 clock, sync reset
din in 1 serial bit per clock
detected out 1 high when the last 3 bits were 110

Tip: keep a tiny shift register of the last few bits, or build it as a small state machine, your choice.

Show the testbench (the grader)
tb.v, locked
`timescale 1ns/1ps
module tb;
    reg clk=0, rst=1, din=0; wire detected;
    reg [2:0] hist = 0; reg want;
    integer i, errors=0; reg [31:0] lfsr = 32'hF00D;
    challenge dut (.clk(clk), .rst(rst), .din(din), .detected(detected));
    always #5 clk = ~clk;
    initial begin
        $dumpfile("wave.vcd"); $dumpvars(0, tb);
        repeat (2) @(negedge clk); rst = 0;
        for (i = 0; i < 400; i = i + 1) begin
            @(negedge clk);
            lfsr = {lfsr[30:0], lfsr[31]^lfsr[21]^lfsr[1]^lfsr[0]};
            din = lfsr[1];
            @(posedge clk);
            hist = {hist[1:0], din};
            want = (hist == 3'b110);
            #1;
            if (detected !== want) begin
                errors = errors + 1;
                if (errors < 6)
                    $display("FAIL @%0t: hist=%b detected=%b want=%b",
                             $time, hist, detected, want);
            end
        end
        if (errors == 0) $display("TB PASS");
        else $display("TB FAIL (%0d errors)", errors);
        $finish;
    end
endmodule