A 4-bit counter: on each clock with en high, count up when
dir=1, down when dir=0, wrapping naturally (15→0 up, 0→15 down).
Synchronous reset to 0. Hold when en is low.
| Port | Dir | Width | Meaning |
|---|---|---|---|
| clk, rst, en, dir | in | 1 | clock, sync reset, enable, 1=up |
| count | out | 4 | the count |
Refresher: the counters lesson.
`timescale 1ns/1ps
module tb;
reg clk=0, rst=1, en=0, dir=1; wire [3:0] count;
reg [3:0] model = 0;
integer i, errors=0; reg [31:0] lfsr = 32'hBEEF;
challenge dut (.clk(clk), .rst(rst), .en(en), .dir(dir), .count(count));
always #5 clk = ~clk;
initial begin
$dumpfile("wave.vcd"); $dumpvars(0, tb);
repeat (2) @(negedge clk); rst = 0;
for (i = 0; i < 300; i = i + 1) begin
@(negedge clk);
lfsr = {lfsr[30:0], lfsr[31]^lfsr[21]^lfsr[1]^lfsr[0]};
en = lfsr[0]; dir = lfsr[1];
@(posedge clk);
if (en) model = dir ? model + 4'd1 : model - 4'd1;
#1;
if (count !== model) begin
errors = errors + 1;
if (errors < 6)
$display("FAIL @%0t: count=%0d want=%0d", $time, count, model);
end
end
if (errors == 0) $display("TB PASS");
else $display("TB FAIL (%0d errors)", errors);
$finish;
end
endmodule