Wire It Up

Implement y = (a AND b) OR (NOT c) as pure combinational logic.

Port	Dir	Width	Meaning
a, b, c	in	1	inputs
y	out	1	`(a & b) \| ~c`

Refresher: the logic gates lesson.

Show the testbench (the grader)

tb.v — locked

`timescale 1ns/1ps
module tb;
    reg a=0, b=0, c=0; wire y; integer i, errors=0;
    challenge dut (.a(a), .b(b), .c(c), .y(y));
    initial begin
        $dumpfile("wave.vcd"); $dumpvars(0, tb);
        for (i = 0; i < 8; i = i + 1) begin
            {a,b,c} = i[2:0]; #5;
            if (y !== ((a & b) | ~c)) begin
                errors = errors + 1;
                $display("FAIL: a=%b b=%b c=%b -> y=%b", a, b, c, y);
            end
        end
        if (errors == 0) $display("TB PASS");
        else $display("TB FAIL (%0d errors)", errors);
        $finish;
    end
endmodule