MyHDL playground

Describe hardware in MyHDL — Python that models real digital circuits — then simulate it and watch the waveform. Runs server-side, no installs. Keep a config_sim(trace=True) + run_sim() and end the stimulus with StopSimulation. Limits: 16 KB, ~5 s, no file or system access.

MyHDL (Python)

# MyHDL: describe hardware in Python, simulate it, see the waveform.
# This 4-bit counter is the same circuit as the Verilog playground's default.
from myhdl import (block, always_seq, always, instance, Signal, modbv,
                   ResetSignal, delay, StopSimulation)

@block
def counter(clk, rst, en, count):
    @always_seq(clk.posedge, reset=rst)
    def logic():
        if en:
            count.next = count + 1
    return logic

@block
def tb():
    clk = Signal(bool(0))
    rst = ResetSignal(0, active=1, isasync=False)
    en  = Signal(bool(0))
    count = Signal(modbv(0)[4:])           # modbv wraps (15 -> 0)

dut = counter(clk, rst, en, count)

@always(delay(5))
    def clkgen():
        clk.next = not clk

@instance
    def stim():
        rst.next = 1
        yield delay(12)
        rst.next = 0
        en.next = 1
        yield delay(160)
        raise StopSimulation
    return dut, clkgen, stim

inst = tb()
inst.config_sim(trace=True)   # emit a VCD we turn into the waveform below
inst.run_sim()

About this tool

MyHDL turns Python into a hardware description language: generators model concurrent processes (like Verilog's always blocks), a Signal class carries values between them, and the same code both simulates (on the Python interpreter, with the full unittest framework available) and converts to Verilog or VHDL for synthesis. This playground runs the simulator and renders the VCD it produces. New to the ideas? The HDL course and the MyHDL introduction explain the concepts; the Verilog playground is the classic-HDL counterpart.