Open-Source FPGA Flow Quickstart

Yosys + nextpnr + iceprog: zero-license, scriptable, fast.

What it is

A fully open toolchain: yosys synthesizes Verilog, nextpnr places and routes, and a small packer/programmer writes the bitstream. First-class targets: Lattice iCE40 (icestorm flow) and ECP5 (prjtrellis flow); Gowin support (apicula) is maturing fast. Compile times are seconds-to-minutes, not minutes-to-hours — a different way of life.

Install (one line each)

# Most distros / brew:
apt install yosys nextpnr-ice40 fpga-icestorm   # Debian/Ubuntu
brew install yosys icestorm && brew install --HEAD nextpnr  # macOS
# Or grab prebuilt: github.com/YosysHQ/oss-cad-suite-build (everything, nightly)

The OSS CAD Suite bundle is the easiest path: yosys, nextpnr, GHDL, Verilator, iverilog and gtkwave in one tarball.

iCE40 flow (e.g. iCEBreaker / iCEstick)

yosys -p 'synth_ice40 -top top -json top.json' top.v
nextpnr-ice40 --up5k --package sg48 --json top.json \
              --pcf top.pcf --asc top.asc
icepack top.asc top.bin
iceprog top.bin

The .pcf pin file is one line per pin: set_io led 39 (generate the XDC/QSF equivalents for vendor tools with our pinout converter).

ECP5 flow (e.g. ULX3S)

yosys -p 'synth_ecp5 -top top -json top.json' top.v
nextpnr-ecp5 --85k --package CABGA381 --json top.json \
             --lpf top.lpf --textcfg top.config
ecppack top.config top.bit
openFPGALoader top.bit

Timing and resource answers

yosys -p 'synth_ice40 -top top; stat'      # LUT/FF/BRAM counts
nextpnr-ice40 ... --freq 48                # ask for 48 MHz...
# nextpnr reports achieved Fmax per clock after routing - honest and fast

Simulation and lint partners

What to know going in