biRISC-V
stableA 32-bit superscalar, dual-issue RISC-V CPU.
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LicenseApache-2.0
Languagesverilog
Interfacesaxi
Targetsdevice-agnostic
Categorycpu
Verification
We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.
- 1,273 GitHub stars
About
biRISC-V is a 32-bit superscalar, dual-issue in-order RISC-V core (RV32IMZicsr) with branch prediction and caches, from ultraembedded. A great step up from a simple single-issue core if you want to study how real performance features like dual issue and prediction fit together.