biRISC-V
stableA 32-bit superscalar, dual-issue RISC-V CPU.
Install with
lfpga
lfpga add biriscv
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Verification
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[](https://libfpga.com/cores/biriscv)
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About
biRISC-V is a 32-bit superscalar, dual-issue in-order RISC-V core (RV32IMZicsr) with branch prediction and caches, from ultraembedded. A great step up from a simple single-issue core if you want to study how real performance features like dual issue and prediction fit together.