FPGA core registry

Verified reusable Verilog building blocks for FPGA designs.

An educational neural network on an FPGA, from a single neuron to an XOR net.

The same building blocks in MyHDL, hardware described in Python.

A high-throughput JPEG decoder in Verilog.

An SDRAM controller with a standard AXI4 interface.

A DDR1 controller that gives low-end FPGAs cheap, large memory.

An FPGA SD-card reader with a FAT file-system layer.

An FPGA-based USB 1.1 full-speed device (no PHY chip).

An SD-card controller supporting SPI, SDIO and eMMC.

A clean Verilog AES block cipher (128/256-bit).

A hardware implementation of the ChaCha stream cipher.

A hardware implementation of the SHA-256 hash function.

A comprehensive set of AXI4 infrastructure components for FPGAs.

Ethernet MAC and UDP/IP stack components in Verilog.

A simple, widely-used Verilog UART with an AXI-Stream interface.

Formally verified Wishbone and AXI bus bridges and utilities.

A basic USB-CDC (serial) device core in Verilog.

A basic USB 1.1 host controller for small systems.

A PDM MEMS microphone interface (PDM to PCM) for FPGAs.

Parameterized IEEE 754 floating-point units (FMA, conversions) in Chisel.

An open, Linux-supported CAN FD controller IP core.

An industrial-grade 32-bit RISC-V embedded core from OpenHW.

A 6-stage 64-bit RISC-V core that boots Linux.

A parametric floating-point unit for RISC-V and transprecision.

A cycle-accurate Motorola 68000 CPU core.

Berkeley's systolic-array generator for ML accelerators.

The 3-stage RISC-V core inside the RP2350.

A small, production 32-bit RISC-V core with serious verification behind it.

NVIDIA's open Deep Learning Accelerator, in RTL.

A size-optimized RISC-V CPU that fits in a corner of your FPGA.

The standard open RISC-V debug module and JTAG transport.

The Chisel generator behind a whole family of RISC-V SoCs.

An FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.

An FPGA-based USB 2.0 high-speed audio interface with ADAT.

A 64-bit RISC-V Vector (RVV) unit from PULP.

A 32-bit superscalar, dual-issue RISC-V CPU.

The standard open-silicon SoC harness for chip tapeouts.

An audio controller: I2S, S/PDIF and DAC output.

An open-source FPGA-based NIC and platform for in-network compute.

A synthesizable IEEE-754 floating-point unit.

A configurable pipelined FFT core generator.

A collection of demonstration digital filters, done rigorously.

A from-scratch DisplayPort implementation for FPGAs.

A lightweight CAN 2.0 bus controller for FPGAs.

FPGA Field-Oriented Control for driving BLDC / PMSM motors.

A lossless JPEG-LS image encoder in Verilog.

A Sega Genesis / Mega Drive core for MiSTer.

Send true HDMI video and audio from an FPGA, no IP licence.

Capture MIPI CSI-2 video from a Raspberry Pi Camera on an FPGA.

A fully pipelined integer radix-2 FFT / IFFT IP core.

Jose Tejada's FPGA-accurate arcade sound and system cores.

A small-footprint, configurable DRAM controller.

A small-footprint, configurable Ethernet core.

A small, configurable on-chip logic analyzer for FPGAs.

Build your hardware easily: a Python-based SoC builder.

An Amaranth framework for building and hacking USB devices.

A sigma-delta audio DAC and PCM player core.

A widely-used MIPI CSI-2 camera sensor receiver in Verilog.

An OpenRISC 1000 processor core.

A customizable MCU-class RISC-V SoC in platform-independent VHDL.

A Nintendo Entertainment System core for MiSTer.

An open GPGPU architecture for graphics and parallel compute.

Open logic-analyzer gateware (SUMP-compatible).

A VHDL IP library with arithmetic units: dividers, square root and prefix adders.

Exciting open-source FPGA graphics and video designs to build on.

A Sony PlayStation core for MiSTer.

Wishbone-controlled SPI and QSPI flash controllers.

A Chisel implementation of the ratified RISC-V Vector 1.0 spec.

A simple, readable SDRAM controller core in VHDL.

The award-winning bit-serial RISC-V: the world's smallest.

An analog-to-digital converter built in FPGA fabric.

A Super Nintendo core for MiSTer.

The Berkeley out-of-order RISC-V machine.

A compact RV32IM RISC-V CPU core in Verilog.

A dual-issue, in-order RISC-V core (formerly SweRV).

PCI Express interface components for FPGAs, in Verilog.

A video display simulator with real VGA/HDMI generation cores.

A small, light, pipelined RISC soft-core with a rigorous pedigree.

Configurable CORDIC core generator for sine, cosine and vector rotation.

A minimal RISC-V core written from scratch in one night.

An open-source silicon root of trust (secure element).

Posit arithmetic core generator: parameterized Verilog adder, multiplier, divider.

Reusable Verilog blocks including pipelined square root and integer divider.

A synthesizable delta-sigma modulator IP core.