A curated directory of open FPGA IP cores, with a quality signal you can trust: many listings carry earned badges from our open toolchain, lints clean, testbench passes, synthesizes, formally proven. Filter by what you actually need.
Phase 0: a hand-curated seed set spanning CPUs, SoCs, interconnect and networking. Badges are shown only where LibFPGA has actually run the checks (our own cores, for now); the rest are marked verification pending. Own one of these repos? Claiming by a manifest file in your repo is on the way.
26 of 26 cores
libfpga
Featured stableVerified reusable Verilog building blocks for FPGA designs.
fpga-neuron
stableA neural network from first principles to FPGA hardware.
libfpga-myhdl
betaThe same building blocks in MyHDL, hardware described in Python.
CV32E40P
productionAn industrial-grade 32-bit RISC-V embedded core from OpenHW.
CVA6 (Ariane)
productionA 6-stage 64-bit RISC-V core that boots Linux.
Hazard3
productionThe 3-stage RISC-V core inside the RP2350.
Ibex
productionA small, production 32-bit RISC-V core with serious verification behind it.
PicoRV32
productionA size-optimized RISC-V CPU that fits in a corner of your FPGA.
Rocket Chip
productionThe Chisel generator behind a whole family of RISC-V SoCs.
VexRiscv
productionAn FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.
Corundum
stableAn open-source FPGA-based NIC and platform for in-network compute.
LiteDRAM
stableA small-footprint, configurable DRAM controller.
LiteEth
stableA small-footprint, configurable Ethernet core.
LiteX
stableBuild your hardware easily: a Python-based SoC builder.
LUNA
stableAn Amaranth framework for building and hacking USB devices.
mor1kx
stableAn OpenRISC 1000 processor core.
NEORV32
stableA customizable MCU-class RISC-V SoC in platform-independent VHDL.
secworks/aes
stableA clean Verilog AES block cipher (128/256-bit).
SERV
stableThe award-winning bit-serial RISC-V: the world's smallest.
SonicBOOM (riscv-boom)
stableThe Berkeley out-of-order RISC-V machine.
verilog-axi
stableA comprehensive set of AXI4 infrastructure components for FPGAs.
verilog-ethernet
stableEthernet MAC and UDP/IP stack components in Verilog.
verilog-pcie
stablePCI Express interface components for FPGAs, in Verilog.
wb2axip
stableFormally verified Wishbone and AXI bus bridges and utilities.
ZipCPU
stableA small, light, pipelined RISC soft-core with a rigorous pedigree.
DarkRISCV
betaA minimal RISC-V core written from scratch in one night.
No cores match those filters. Clear.