Caravel
stableThe standard open-silicon SoC harness for chip tapeouts.
lfpga add caravel
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[](https://libfpga.com/cores/caravel)
- 400 GitHub stars
About
Caravel is the SoC harness at the heart of the open-silicon movement: a management RISC-V core, wishbone bus, and a padframe wrapping a user project area, the template used for hundreds of real chip tapeouts on SkyWater and GlobalFoundries via Efabless. If you want to tape out an FPGA-proven design to actual silicon, this is where it starts.