core_sdram_axi4
stableAn SDRAM controller with a standard AXI4 interface.
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LicenseGPL-3.0
Languagesverilog
Interfacesaxi4
Targetsdevice-agnostic
Categorymemory
Verification
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- 105 GitHub stars
About
An SDR SDRAM controller from ultraembedded that presents a clean AXI4 slave interface, so it drops straight into an AXI-based SoC. Comes with a C++ reference model for verification, a nice example of pairing RTL with a software golden model.