core_sdram_axi4
stableAn SDRAM controller with a standard AXI4 interface.
Install with
lfpga
lfpga add core-sdram-axi4
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Verification
Signals earned by running the open toolchain against the public source. This listing is not yet owner-claimed; the badges reflect our build, not a maintainer's declaration. This is the registry's whole point: know it works before you clone it.
✓ Lints clean
Testbench passes
✓ Synthesizes
Formally proven
Converts to RTL
Last checked 2026-07-05 by the LibFPGA toolchain.
[](https://libfpga.com/cores/core-sdram-axi4)
- 807 LUT4s
- 105 GitHub stars
About
An SDR SDRAM controller from ultraembedded that presents a clean AXI4 slave interface, so it drops straight into an AXI-based SoC. Comes with a C++ reference model for verification, a nice example of pairing RTL with a software golden model.