CVA6 (Ariane)

production

A 6-stage 64-bit RISC-V core that boots Linux.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseSolderpad-0.51
Languagessystemverilog
Interfacesaxi4
Targetsdevice-agnostic
Categorycpu

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

About

The CORE-V CVA6 (originally Ariane) is a configurable, application-class 64-bit RISC-V core with a 6-stage pipeline, MMU and caches, capable of booting Linux. Governed by the OpenHW Group with an industrial verification effort, it targets both FPGA prototyping and ASIC, and anchors the CORE-V family of open cores. An AXI4 master interface makes it straightforward to drop into a larger SoC.

risc-vcpurv64linuxapplication-classopenhw