DarkRISCV

beta

A minimal RISC-V core written from scratch in one night.

Install with lfpga lfpga add darkriscv

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseBSD-3-Clause
Languagesverilog
Targetsdevice-agnostic
CategoryCPU

Source on GitHub →

Verification

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About

A compact RV32E/RV32I core famously written from scratch in a single night, then polished into a genuinely usable and readable design. Its small, approachable codebase makes it a favourite for learning how a pipelined RISC-V actually works, and it still runs real code on real FPGAs.

risc-vcpurv32minimaleducational

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