DarkRISCV
betaA minimal RISC-V core written from scratch in one night.
Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.
LicenseBSD-3-Clause
Languagesverilog
Targetsdevice-agnostic
Categorycpu
Verification
We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.
- 2,581 GitHub stars
About
A compact RV32E/RV32I core famously written from scratch in a single night, then polished into a genuinely usable and readable design. Its small, approachable codebase makes it a favourite for learning how a pipelined RISC-V actually works, and it still runs real code on real FPGAs.