dblclockfft
stableA configurable pipelined FFT core generator.
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LicenseLGPL-3.0
Languagesverilog
Targetsdevice-agnostic
Categorydsp
Source on GitHub → Docs / homepage
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- 262 GitHub stars
About
A generator (from ZipCPU) that emits a configurable, fully pipelined FFT in Verilog for any power-of-two size and bit width, processing two samples per clock. The companion writeups are some of the best FFT-in-hardware teaching material anywhere.