FPGA-DDR-SDRAM
stableA DDR1 controller that gives low-end FPGAs cheap, large memory.
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LicenseGPL-3.0
Languagesverilog
Interfacesaxi4
Targetsdevice-agnostic
Categorymemory
Verification
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- 217 GitHub stars
About
A compact DDR1 SDRAM controller aimed at low-end FPGA embedded systems, giving them access to cheap, high-capacity external memory with a simple read/write interface. A practical option when your board has DDR1 and your FPGA has no hardened memory controller.