Hazard3

production

The 3-stage RISC-V core inside the RP2350.

Install with lfpga lfpga add hazard3

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LicenseApache-2.0
Languagesverilog
Interfacesahb-lite
Targetsdevice-agnostic
CategoryCPU

Source on GitHub →

Verification

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About

A configurable 3-stage RV32IMACZb* core with full debug support, notable for being the open RISC-V CPU shipped in Raspberry Pi's RP2350. Proof that a clean, readable open core can end up in a mass-market silicon product.

risc-vcpurv32rp2350debug

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