Hazard3

production

The 3-stage RISC-V core inside the RP2350.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseApache-2.0
Languagesverilog
Interfacesahb-lite
Targetsdevice-agnostic
Categorycpu

Source on GitHub →

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

About

A configurable 3-stage RV32IMACZb* core with full debug support, notable for being the open RISC-V CPU shipped in Raspberry Pi's RP2350. Proof that a clean, readable open core can end up in a mass-market silicon product.

risc-vcpurv32rp2350debug