libfpga

Featured stable

Verified reusable Verilog building blocks for FPGA designs.

✓ Claimed by @libfpga. This listing is owner-controlled via a libfpga.yaml manifest in the repository.

LicenseMIT
Languagesverilog
Interfacesaxi4-lite, uart, spi, i2c
Targetsdevice-agnostic
Categorylibrary

Source on GitHub → Docs / homepage

Verification

Signals earned by running the open toolchain. This is the registry's whole point: know it works before you clone it.

✓ Lints clean ✓ Testbench passes ✓ Synthesizes ✓ Formally proven Converts to RTL

Last checked 2026-07-04 by the LibFPGA toolchain.

Runs our toolchain against your declared sources.

About

A growing library of small, sharp, independently verified Verilog modules: CDC primitives, sync and async FIFOs, a skid buffer, round-robin arbiter, UART/SPI/I2C, CRC and LFSR, a fixed-point and neural micro-kit (MAC, ReLU, an MLP generator), and an AXI4-Lite bridge. Every module ships with a self-checking testbench, is Verilator -Wall clean, carries honest Yosys resource numbers, and the safety-critical blocks are formally proven by induction. 29 modules, all green in CI.

cdcfifouartspii2ccrclfsraxiarbiterfixed-pointneural