mor1kx

stable

An OpenRISC 1000 processor core.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseCERN-OHL-W-2.0
Languagesverilog
Interfaceswishbone
Targetsdevice-agnostic
Categorycpu

Source on GitHub →

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

About

A configurable OpenRISC 1000 (or1k) CPU with selectable pipeline implementations, the mature reference core of the OpenRISC project. A well-established, Linux-capable alternative to the RISC-V cores for anyone in the OpenRISC ecosystem.

openrisccpuor1kwishbone