SonicBOOM (riscv-boom)

stable

The Berkeley out-of-order RISC-V machine.

Install with lfpga lfpga add riscv-boom

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseBSD-3-Clause
Languageschisel
Targetsdevice-agnostic
CategoryCPU

Verification

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About

An open superscalar, out-of-order RISC-V core built in Chisel on top of the Rocket ecosystem. BOOM is where you go to study serious high-performance microarchitecture in the open: branch prediction, register renaming, and speculative execution, all readable.

risc-vcpuout-of-ordersuperscalarchisel