SonicBOOM (riscv-boom)

stable

The Berkeley out-of-order RISC-V machine.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseBSD-3-Clause
Languageschisel
Targetsdevice-agnostic
Categorycpu

Source on GitHub →

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

About

An open superscalar, out-of-order RISC-V core built in Chisel on top of the Rocket ecosystem. BOOM is where you go to study serious high-performance microarchitecture in the open: branch prediction, register renaming, and speculative execution, all readable.

risc-vcpuout-of-ordersuperscalarchisel