riscv-dbg
productionThe standard open RISC-V debug module and JTAG transport.
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LicenseSolderpad-0.51
Languagessystemverilog
Interfacesaxi4
Targetsdevice-agnostic
Categorydebug
Verification
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- 314 GitHub stars
About
A compliant implementation of the RISC-V Debug specification: the Debug Module plus a JTAG Debug Transport Module, letting a host debugger halt, inspect, and single-step a RISC-V core over JTAG. From the PULP platform and used across many open and commercial RISC-V designs, it is the de-facto standard way to make an open core debuggable.