Rocket Chip

production

The Chisel generator behind a whole family of RISC-V SoCs.

Install with lfpga lfpga add rocket-chip

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseApache-2.0
Languageschisel
Interfacesaxi4
Targetsdevice-agnostic
CategoryCPU

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

Maintain this core? Add the badge: lfpga registry status [![lfpga](https://libfpga.com/cores/rocket-chip/badge.svg)](https://libfpga.com/cores/rocket-chip)

About

Not a single core but a generator: parameterized Chisel that emits complete RISC-V systems, from the in-order Rocket core to caches, TileLink interconnect and peripherals. It underpins much of the academic and commercial RISC-V ecosystem and is the canonical example of generator-based hardware design.

risc-vcpugeneratorchiseltilelinksoc