Rocket Chip
productionThe Chisel generator behind a whole family of RISC-V SoCs.
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LicenseApache-2.0
Languageschisel
Interfacesaxi4
Targetsdevice-agnostic
Categorycpu
Verification
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- 3,807 GitHub stars
About
Not a single core but a generator: parameterized Chisel that emits complete RISC-V systems, from the in-order Rocket core to caches, TileLink interconnect and peripherals. It underpins much of the academic and commercial RISC-V ecosystem and is the canonical example of generator-based hardware design.