sdram-fpga
stableA simple, readable SDRAM controller core in VHDL.
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LicenseMIT
Languagesvhdl
Targetsdevice-agnostic
Categorymemory
Verification
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- 126 GitHub stars
About
A clean, well-documented SDRAM controller in VHDL, popular in arcade and retro FPGA projects for its readability. A great reference if you want to understand how an SDRAM controller sequences refresh, activate, and read/write commands.