SERV

stable

The award-winning bit-serial RISC-V: the world's smallest.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseISC
Languagesverilog
Interfaceswishbone
Targetsdevice-agnostic
Categorycpu

Source on GitHub →

Verification

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About

A bit-serial RISC-V core that processes one bit per cycle, trading throughput for an astonishingly small footprint (often a few hundred LUTs). Perfect where you need a real CPU in almost no area, for control, sequencing, or massively replicated compute. Packaged with FuseSoC and a frequent teaching example of extreme area optimization.

risc-vcpubit-serialsmallestfusesoc