SV_DSM_CORE
betaA synthesizable delta-sigma modulator IP core.
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LicenseMIT
Languagessystemverilog
Targetsdevice-agnostic
Categorysensor
Verification
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- 2 GitHub stars
About
A clean, parameterized SystemVerilog IP core for a delta-sigma modulator, the mathematical heart of both sigma-delta ADCs and DACs. A reusable, MIT-licensed building block if you want to compose your own analog interface rather than drop in a fixed converter.