ultraembedded/riscv
stableA compact RV32IM RISC-V CPU core in Verilog.
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LicenseBSD-3-Clause
Languagesverilog
Interfacesaxi
Targetsdevice-agnostic
Categorycpu
Verification
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- 1,748 GitHub stars
About
A small, readable RV32IM RISC-V core with caches and an AXI interface, one of the most-cloned single-issue RISC-V cores on GitHub. A friendly starting point for building your own SoC or just learning how a RISC-V pipeline hangs together.