core_usb_cdc

beta

A basic USB-CDC (serial) device core in Verilog.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseLGPL-2.1
Languagesverilog
Interfacesusb
Targetsdevice-agnostic
Categoryusb

Source on GitHub →

Verification

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About

A compact USB full-speed CDC (communications device class) core, giving an FPGA a USB serial port the host sees as a plain COM/tty device. A practical way to add USB connectivity without an external UART bridge chip.

usbcdcserialdevice