core_usb_cdc

beta

A basic USB-CDC (serial) device core in Verilog.

Install with lfpga lfpga add usb-cdc

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseLGPL-2.1
Languagesverilog
Interfacesusb
Targetsdevice-agnostic
CategoryUSB

Source on GitHub →

Verification

Signals earned by running the open toolchain against the public source. This listing is not yet owner-claimed; the badges reflect our build, not a maintainer's declaration. This is the registry's whole point: know it works before you clone it.

✓ Lints clean Testbench passes ✓ Synthesizes Formally proven Converts to RTL

Last checked 2026-07-05 by the LibFPGA toolchain.

Maintain this core? Add the badge: lfpga registry status [![lfpga](https://libfpga.com/cores/usb-cdc/badge.svg)](https://libfpga.com/cores/usb-cdc)

About

A compact USB full-speed CDC (communications device class) core, giving an FPGA a USB serial port the host sees as a plain COM/tty device. A practical way to add USB connectivity without an external UART bridge chip.

usbcdcserialdevice

Related cores

FPGA-USB-Device ✓ An FPGA-based USB 1.1 full-speed device (no PHY chip). usb · ★ 906 core_usb_host ✓ A basic USB 1.1 host controller for small systems. usb · ★ 100 LUNA An Amaranth framework for building and hacking USB devices. usb · ★ 1,126 libfpga ✓ Verified reusable Verilog building blocks for FPGA designs. library libfpga-myhdl ✓ The same building blocks in MyHDL, hardware described in Python. library verilog-uart ✓ A simple, widely-used Verilog UART with an AXI-Stream interface. interconnect · ★ 574