VeeR EH1

stable

A dual-issue, in-order RISC-V core (formerly SweRV).

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseApache-2.0
Languagessystemverilog
Interfacesaxi, ahb
Targetsdevice-agnostic, asic
Categorycpu

Source on GitHub →

Verification

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About

VeeR EH1 (the core formerly known as Western Digital's SweRV) is a production-grade 32-bit dual-issue, nine-stage RISC-V core now stewarded by CHIPS Alliance. Silicon-proven and well documented, it is one of the strongest open cores for embedded control and storage workloads.

risc-vveerswervcpu