verilog-axi

stable

A comprehensive set of AXI4 infrastructure components for FPGAs.

Install with lfpga lfpga add verilog-axi

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseMIT
Languagesverilog
Interfacesaxi4, axi4-lite
Targetsdevice-agnostic
Categoryinterconnect

Source on GitHub →

Verification

Signals earned by running the open toolchain against the public source. This listing is not yet owner-claimed; the badges reflect our build, not a maintainer's declaration. This is the registry's whole point: know it works before you clone it.

✓ Lints clean Testbench passes ✓ Synthesizes Formally proven Converts to RTL

Last checked 2026-07-05 by the LibFPGA toolchain.

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About

A thorough kit of AXI4 building blocks: crossbar interconnects, width and clock-domain adapters, register slices, DMA, RAM models and AXI-Lite bridges, all in clean parameterized Verilog with cocotb testbenches. If you are wiring an AXI-based SoC on an FPGA, this is one of the most-used open toolboxes for the plumbing.

axiinterconnectdmacrossbarinfrastructure

Related cores

verilog-pcie PCI Express interface components for FPGAs, in Verilog. interconnect · ★ 1,619 wb2axip ✓ Formally verified Wishbone and AXI bus bridges and utilities. interconnect · ★ 684 verilog-uart ✓ A simple, widely-used Verilog UART with an AXI-Stream interface. interconnect · ★ 574 libfpga ✓ Verified reusable Verilog building blocks for FPGA designs. library

Tools for this

Register Map / CSR Generator Describe your registers in text; get an AXI-Lite slave, C header and docs.