verilog-axi
stableA comprehensive set of AXI4 infrastructure components for FPGAs.
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LicenseMIT
Languagesverilog
Interfacesaxi4, axi4-lite
Targetsdevice-agnostic
Categoryinterconnect
Verification
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About
A thorough kit of AXI4 building blocks: crossbar interconnects, width and clock-domain adapters, register slices, DMA, RAM models and AXI-Lite bridges, all in clean parameterized Verilog with cocotb testbenches. If you are wiring an AXI-based SoC on an FPGA, this is one of the most-used open toolboxes for the plumbing.