verilog-ethernet
stableEthernet MAC and UDP/IP stack components in Verilog.
lfpga add verilog-ethernet
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Last checked 2026-07-05 by the LibFPGA toolchain.
[](https://libfpga.com/cores/verilog-ethernet)
- 405 LUT4s
- 3,018 GitHub stars
About
Synthesizable Ethernet components from the MAC up through a lightweight UDP/IP stack, covering 10M to 10G with AXI-Stream interfaces and cocotb verification. A go-to for getting packets on and off an FPGA without licensing a vendor MAC, and a clean study in streaming datapath design.