verilog-ethernet
stableEthernet MAC and UDP/IP stack components in Verilog.
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LicenseMIT
Languagesverilog
Interfacesaxi-stream
Targetsdevice-agnostic
Categorynetworking
Verification
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- 3,018 GitHub stars
About
Synthesizable Ethernet components from the MAC up through a lightweight UDP/IP stack, covering 10M to 10G with AXI-Stream interfaces and cocotb verification. A go-to for getting packets on and off an FPGA without licensing a vendor MAC, and a clean study in streaming datapath design.