verilog-pcie

stable

PCI Express interface components for FPGAs, in Verilog.

Install with lfpga lfpga add verilog-pcie

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseMIT
Languagesverilog
Interfacespcie, axi4, axi-stream
Targetsultrascale
Categoryinterconnect

Source on GitHub →

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

Maintain this core? Add the badge: lfpga registry status [![lfpga](https://libfpga.com/cores/verilog-pcie/badge.svg)](https://libfpga.com/cores/verilog-pcie)

About

A thorough toolbox of PCI Express building blocks: DMA engines, AXI and AXI-Stream adapters, and the glue to bridge a vendor's hard PCIe block into your datapath, all in clean parameterized Verilog with cocotb tests. The companion to verilog-axi and the backbone of projects like Corundum.

pciedmainterconnectinfrastructure

Related cores

verilog-axi ✓ A comprehensive set of AXI4 infrastructure components for FPGAs. interconnect · ★ 2,082 wb2axip ✓ Formally verified Wishbone and AXI bus bridges and utilities. interconnect · ★ 684 verilog-uart ✓ A simple, widely-used Verilog UART with an AXI-Stream interface. interconnect · ★ 574 Corundum An open-source FPGA-based NIC and platform for in-network compute. networking · ★ 2,384

Tools for this

Register Map / CSR Generator Describe your registers in text; get an AXI-Lite slave, C header and docs.