verilog-pcie
stablePCI Express interface components for FPGAs, in Verilog.
Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.
LicenseMIT
Languagesverilog
Interfacespcie, axi4, axi-stream
Targetsultrascale
Categoryinterconnect
Verification
We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.
- 1,619 GitHub stars
About
A thorough toolbox of PCI Express building blocks: DMA engines, AXI and AXI-Stream adapters, and the glue to bridge a vendor's hard PCIe block into your datapath, all in clean parameterized Verilog with cocotb tests. The companion to verilog-axi and the backbone of projects like Corundum.