verilog-uart

stable

A simple, widely-used Verilog UART with an AXI-Stream interface.

Install with lfpga lfpga add verilog-uart

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseMIT
Languagesverilog
Interfacesuart
Targetsdevice-agnostic
Categoryinterconnect

Source on GitHub →

Verification

Signals earned by running the open toolchain against the public source. This listing is not yet owner-claimed; the badges reflect our build, not a maintainer's declaration. This is the registry's whole point: know it works before you clone it.

✓ Lints clean Testbench passes ✓ Synthesizes Formally proven Converts to RTL

Last checked 2026-07-05 by the LibFPGA toolchain.

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About

A clean, parameterizable UART in Verilog with an AXI-Stream interface, from Alex Forencich's widely-used component collection. A dependable drop-in when you just need reliable serial I/O without reinventing the state machine.

uartserialaxi-streamperipheral

Related cores

verilog-axi ✓ A comprehensive set of AXI4 infrastructure components for FPGAs. interconnect · ★ 2,082 wb2axip ✓ Formally verified Wishbone and AXI bus bridges and utilities. interconnect · ★ 684 verilog-pcie PCI Express interface components for FPGAs, in Verilog. interconnect · ★ 1,619 libfpga ✓ Verified reusable Verilog building blocks for FPGA designs. library libfpga-myhdl ✓ The same building blocks in MyHDL, hardware described in Python. library core_usb_cdc ✓ A basic USB-CDC (serial) device core in Verilog. usb · ★ 91

Tools for this

UART Baud Rate Calculator Clock divisor, real baud rate and error % for any clock/baud pair. Register Map / CSR Generator Describe your registers in text; get an AXI-Lite slave, C header and docs.