verilog-uart
stableA simple, widely-used Verilog UART with an AXI-Stream interface.
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LicenseMIT
Languagesverilog
Interfacesuart
Targetsdevice-agnostic
Categoryinterconnect
Verification
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- 574 GitHub stars
About
A clean, parameterizable UART in Verilog with an AXI-Stream interface, from Alex Forencich's widely-used component collection. A dependable drop-in when you just need reliable serial I/O without reinventing the state machine.