VexRiscv
productionAn FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.
Install with
lfpga
lfpga add vexriscv
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Verification
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[](https://libfpga.com/cores/vexriscv)
- 3,181 GitHub stars
About
A 32-bit RISC-V core assembled from plugins in SpinalHDL, so you compose exactly the pipeline, caches, MMU and buses you need, from a tiny microcontroller up to a Linux-capable configuration. It generates clean Verilog or VHDL for a standard flow and is widely deployed on real FPGAs. A showcase of what a modern, generator-based HDL brings to core design.