VexRiscv
productionAn FPGA-friendly, highly configurable 32-bit RISC-V, built in SpinalHDL.
Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.
LicenseMIT
Languagesspinalhdl
Interfacesaxi4, apb, wishbone
Targetsdevice-agnostic
Categorycpu
Verification
We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.
- 3,181 GitHub stars
About
A 32-bit RISC-V core assembled from plugins in SpinalHDL, so you compose exactly the pipeline, caches, MMU and buses you need, from a tiny microcontroller up to a Linux-capable configuration. It generates clean Verilog or VHDL for a standard flow and is widely deployed on real FPGAs. A showcase of what a modern, generator-based HDL brings to core design.