wb2axip
stableFormally verified Wishbone and AXI bus bridges and utilities.
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LicenseApache-2.0
Languagesverilog
Interfacesaxi4, axi4-lite, wishbone
Targetsdevice-agnostic
Categoryinterconnect
Verification
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- 684 GitHub stars
About
A collection of bus bridges and interconnect utilities from ZipCPU: Wishbone-to-AXI, AXI-Lite crossbars, data movers, clock crossers and more. Its calling card is rigour, the components come with formal proofs (SymbiYosys) of their bus-protocol correctness, making them unusually trustworthy plumbing for a real SoC.