wb2axip

stable

Formally verified Wishbone and AXI bus bridges and utilities.

Install with lfpga lfpga add wb2axip

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseApache-2.0
Languagesverilog
Interfacesaxi4, axi4-lite, wishbone
Targetsdevice-agnostic
Categoryinterconnect

Source on GitHub →

Verification

Signals earned by running the open toolchain against the public source. This listing is not yet owner-claimed; the badges reflect our build, not a maintainer's declaration. This is the registry's whole point: know it works before you clone it.

✓ Lints clean Testbench passes ✓ Synthesizes Formally proven Converts to RTL

Last checked 2026-07-05 by the LibFPGA toolchain.

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About

A collection of bus bridges and interconnect utilities from ZipCPU: Wishbone-to-AXI, AXI-Lite crossbars, data movers, clock crossers and more. Its calling card is rigour, the components come with formal proofs (SymbiYosys) of their bus-protocol correctness, making them unusually trustworthy plumbing for a real SoC.

axiwishbonebridgeformalinterconnect

Related cores

verilog-axi ✓ A comprehensive set of AXI4 infrastructure components for FPGAs. interconnect · ★ 2,082 verilog-pcie PCI Express interface components for FPGAs, in Verilog. interconnect · ★ 1,619 verilog-uart ✓ A simple, widely-used Verilog UART with an AXI-Stream interface. interconnect · ★ 574 ZipCPU A small, light, pipelined RISC soft-core with a rigorous pedigree. cpu · ★ 1,558 libfpga ✓ Verified reusable Verilog building blocks for FPGA designs. library sdspi ✓ An SD-card controller supporting SPI, SDIO and eMMC. memory · ★ 390

Tools for this

Register Map / CSR Generator Describe your registers in text; get an AXI-Lite slave, C header and docs.