ZipCPU

stable

A small, light, pipelined RISC soft-core with a rigorous pedigree.

Indexed from a public source and curated by LibFPGA. Own this project? Claim it by adding a manifest file to your repo.

LicenseGPL-3.0
Languagesverilog
Interfaceswishbone, axi4
Targetsdevice-agnostic
Categorycpu

Source on GitHub → Docs / homepage

Verification

We have not run this core through the LibFPGA toolchain yet, so it carries no earned badges. Many of these projects have strong verification of their own. Claim the listing to run our checks.

About

A compact 32-bit RISC CPU from the author of the widely respected ZipCPU blog, built with an emphasis on formal verification and clean bus behaviour. It is small enough for real FPGA use, well documented, and a superb study in how to design and prove a CPU properly.

cpuriscpipelinedwishboneformal