FPGA glossary
The vocabulary of FPGA design, explained in a paragraph or three, each entry linked to the tools and lessons where you can see the concept in action.
Bitstream
The file that programs the FPGA.
Block RAM (BRAM)
Dedicated on-chip memory blocks.
Clock Domain Crossing (CDC)
Moving signals safely between clocks.
Constraint
Telling the tools your design's physical truth.
DSP Slice
The hardened multiply-accumulate engine.
Flip-Flop
One bit of memory, updated on a clock edge.
Fmax
The fastest clock your design can close timing at.
HLS (High-Level Synthesis)
C/C++ in, RTL out.
LUT (Lookup Table)
The FPGA's universal logic gate.
Metastability
When a flip-flop can't decide.
Place & Route
Deciding where logic lives and how wires run.
PLL / MMCM
On-chip clock synthesis.
Setup & Hold Time
The keep-out window around a clock edge.
Soft-Core CPU
A processor built from fabric.
Synthesis
From RTL to a netlist of primitives.
Testbench
The code that tests your code.
Timing Closure
Making every path meet its deadline.
Transceiver (SerDes)
Multi-gigabit serial I/O.